1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device having memory cells vertically-stacked on a substrate and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device is a memory device which is capable of maintaining data stored therein without a power supply. A variety of nonvolatile memory devices such as a flash memory device, are widely being used.
As higher integration of a two-dimensional (2D) memory device having a single layer of memory cells formed on a silicon substrate is reaching physical limits, a three-dimensional (3D) nonvolatile memory device having a plurality of memory cells vertically-stacked on a silicon substrate is being developed.
FIG. 1 is a cross-sectional view of a conventional 3D nonvolatile memory device.
Referring to FIG. 1, the conventional 3D nonvolatile memory device includes a plurality of memory cells (MC) vertically stacked on a substrate, and the memory cells MC are coupled in series between selection transistors LST and UST to form one memory cell string. That is, the selection transistors LST and UST are disposed at the bottom and top of the memory cells MC, respectively.
The lower selection transistor LST includes a lowermost gate electrode layer of a plurality of gate electrode layers 120, a memory layer 130, and a channel layer 140. The upper selection transistor UST includes an uppermost gate electrode layer of the plurality of gate electrode layers 120, the memory layer 130, and the channel layer 140. The plurality of memory cells MC includes the memory layer 130, the channel layer 140, and the plurality of gate electrode layer 120 other than the lowermost and uppermost gate electrode layers, respectively.
Such a 3D nonvolatile memory device may be formed by the series of following processes. First, a plurality of interlayer dielectric layers 110 and gate electrode layers 120 are alternately stacked over the substrate 100. The stacked structure is selectively etched to form a plurality of trenches to expose the substrate 100. The memory layer 130 is formed on sidewalls of each trench, and the trench having the memory layer 130 formed therein is filled with the channel layer 140.
Meanwhile, each of the gate electrode layers 120 may be coupled to a corresponding interconnection line, for example, a source selection line, a drain selection line, a word line, or the like. For this structure, a contact which is not illustrated may be formed on the gate electrode layer 120. In order to secure such a contact formation region, an etching process called a slimming process is performed on the stacked structure of the interlayer dielectric layers 110 and the gate electrode layers 120. When the slimming process is performed, a side portion of the stacked structure of the interlayer dielectric layers 110 and the gate electrode layers 120 is formed in a stepped shape as a whole. Therefore, each of the gate electrode layers 120 is extended more than the one positioned immediately above. Contacts may be formed on the protruding ends of the gate electrode layers 120.
However, the conventional 3D nonvolatile memory device may have the following features.
As illustrated in FIG. 1, the gate electrode layer 120 of the upper selection transistors UST or the gate electrode layer 120 of the lower selection transistors LST has a larger thickness than the gate electrode layer 120 of each memory cell MC. In the 3D structure, the thickness of the gate electrode layer 120 corresponds to the gate length of a transistor. Therefore, in order to enhance an off-leakage current characteristic, the thickness of the gate electrode layers 120 of the upper and lower selection transistors LST and UST is increased.
In such a case, however, since the gate electrode layers 120 of the upper and lower selection transistors LST and UST and the gate electrodes 120 of the memory cells MC are to be deposited by different deposition equipments, the deposition process may be complicated and the process time may increase.
Furthermore, since it is relatively difficult to etch the gate electrode layers 120 of the lower and upper selection transistors LST and UST having a large thickness during the slimming process, a variety of errors may occur in the etching process. In order to prevent such an occurrence of etching defects, the etching process is to be performed by using an additional mask. This may make the entire process complex.
Nevertheless, when the thickness of the gate electrode layers 120 of the lower and upper selection transistors LST and UST is reduced, the above-described off-leakage current characteristic may decrease.